Cerny's patent hints wrong TFlop calculations formula being used

[Playstation Tablet 1,725]

 

 

Basically, Mr. Cerney (@cerny) customized PS5 APU very in depth to its throughput and legancy (and even a cache). Another word, re-writing the “Teraflop” equation: # of shaders * GPU Clock Speed * Instruction Per Clock (usually 2, but here it could be 3)/1000000= Teraflops

 

 

 

So if this is true, the 36 CU @ 2ghz hits 13.8 tflops. So even downclocking from 2ghz would give a good number. Anyways we could be getting more than 2 instructions per clock throwing out the current math we have for the 36CU part.

 

Edited January 11, 2020 by Team 2019

[Playstation Tablet 1,725]

From Intel slide, seems to depend on the task.

 

[Teh_Diplomat 2,054]

[Playstation Tablet 1,725]

Its possible they were always going for 36 CUs for PS4 BC, so they're taking a different approach to their design on the GPU front.

Edited January 11, 2020 by Team 2019

[DynamiteCop 2,086]

That doesn't mean it can execute more, it still has the same FP32 throughput but it can simply fit several smaller things into a single instruction which allows instruction diversification. This is really like a custom play on FP16. The system would still be 9.2 Teraflops, this doesn't change that. 

Edited January 11, 2020 by DynamiteCop!

[Cell 421]

5 minutes ago, DynamiteCop! said:

That doesn't mean it can execute more, it still has the same FP32 throughput but it can simply fit several smaller things into a single instruction which allows instruction diversification. This is really like a custom play on FP16. The system would still be 9.2 Teraflops, this doesn't change that. 

Edited with appropriate smilie.

[Remij 4,679]

lol